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tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras rev. 03 12 september 2002 preliminary data 1. description the tda9962 is a 12-bit analog-to-digital interface for ccd cameras. the device includes a correlated double sampling circuit, pga, clamp loops and a low-power 12-bit adc together with its reference voltage regulator. an internal cds input buffer is incorporated in order to avoid using an external buffer that would consume more power and therefore optimizing the application for low noise, low power working. the pga gain and the adc input clamp level are controlled via the serial interface. an additional dac is provided for additional system controls; its output voltage range is 1.0 v (p-p) which is available at pin ofdout. 2. features n internal cds input buffer, correlated double sampling (cds), programmable gain ampli?er (pga), 12-bit analog-to-digital converter (adc) and reference regulator included n fully programmable via a 3-wire serial interface n sampling frequency up to 30 mhz n pga gain range of 36 db (in steps of 0.1 db) n low power consumption of only 115 mw at 2.7 v n power consumption in standby mode of 4.5 mw (typ.) n 3.0 v operation and 2.2 to 3.6 v operation for the digital outputs n all digital inputs accept 5 v signals n active control pulses polarity selectable via serial interface n 8-bit dac included for analog settings n ttl compatible inputs, cmos compatible outputs. 3. applications n low-power, low-voltage ccd camera systems.
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 2 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. 4. quick reference data 5. ordering information table 1: quick reference data symbol parameter conditions min typ max unit v cca analog supply voltage 2.7 3.0 3.6 v v ccd digital supply voltage 2.7 3.0 3.6 v v cco digital outputs supply voltage 2.2 2.5 3.6 v i cca analog supply current all clamps active - 41 - ma i ccd digital supply current - 2.0 - ma i cco digital outputs supply current f pix = 30 mhz; c l = 10 pf; input ramp of 800 m s duration - 0.5 - ma adc res adc resolution - 12 - bits v i(cds)(p-p) maximum cds input voltage (peak-to-peak value) v cc = 2.85 v 650 -- mv v cc 3 3.0 v 800 -- mv f pix(max) maximum pixel rate 25 -- mhz f pix(min) minimum pixel rate o ccd(max) = 100 mv -- 1 mhz o ccd(max) = 200 mv -- 2 mhz dr pga pga dynamic range - 24 - db n tot(rms) total noise from cds input to adc output pga code = 00; see figure 8 - 1.4 - lsb e in(rms) equivalent input noise (rms value) pga code = 255 - 125 -m v p tot total power consumption v cca =v ccd =3v; v cco = 2.5 v - 130 - mw v cca =v ccd = 2.7 v; v cco = 2.2 v - 115 - mw table 2: ordering information type number package name description version pixel frequency tda9962hl lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 30 mhz
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. preliminary data rev. 03 12 september 2002 3 of 24 6. block diagram fig 1. block diagram. fce504 12-bit adc regulator cds clock generator blanking output buffer 37 38 27 28 29 30 31 32 33 34 35 36 39 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 ognd2 25 26 d1 d0 23 24 v cco1 10 dclpc 21 v ccd1 v cco2 22 dgnd1 3 agnd2 7 v cca2 9 cpcds2 8 cpcds1 4 in 5 agnd3 11 ofdout 14 v cca3 v cca4 v cca5 25, 26 n.c. oe 43 blk 47 clk 40 agnd6 2 agnd1 1 v cca1 41 v cca6 48 clpdm 44 clpob 45 shp shift correlated double sampling 7-bit register 9-bit register 8-bit register 16 15 12 6 13 test agnd4 agnd5 46 shd serial interface 17 18 19 sen sclk sdata 20 vsync 42 stdby pga clamp input buffer v ref ofd dac data flip- flop clamp tda9962 ognd1 black level shift
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 4 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin con?guration. 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 12 24 37 25 tda9962hl fce505 d9 d10 d11 d8 d7 d6 d4 d3 d2 d1 d0 v cca1 v cca2 agnd1 agnd2 in agnd3 agnd4 cpcds1 cpcds2 ofdout test d5 clk shd shp clpob blk stdby agnd6 ognd2 oe clpdm v cca6 v cco2 dclpc agnd5 v cca3 v cca4 v cca5 v ccd1 v cco1 dgnd1 sclk sen ognd1 vsync s data table 3: pin description symbol pin description v cca1 1 analog supply voltage 1 agnd1 2 analog ground 1 agnd2 3 analog ground 2 in 4 input signal from ccd agnd3 5 analog ground 3 agnd4 6 analog ground 4 v cca2 7 analog supply voltage 2 cpcds1 8 clamp storage capacitor pin 1 cpcds2 9 clamp storage capacitor pin 2 dclpc 10 regulator decoupling pin ofdout 11 analog output of the additional 8-bit control dac test 12 test mode input pin (should be connected to agnd5) agnd5 13 analog ground 5 v cca3 14 analog supply voltage 3
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 5 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. v cca4 15 analog supply voltage 4 v cca5 16 analog supply voltage 5 sdata 17 serial data input for serial interface control sclk 18 serial clock input for serial interface sen 19 strobe pin for serial interface vsync 20 vertical sync pulse input v ccd1 21 digital supply voltage 1 dgnd1 22 digital ground 1 v cco1 23 digital outputs supply voltage 1 ognd1 24 digital output ground 1 d0 25 adc digital output 0 (lsb) d1 26 adc digital output 1 d2 27 adc digital output 2 d3 28 adc digital output 3 d4 29 adc digital output 4 d5 30 adc digital output 5 d6 31 adc digital output 6 d7 32 adc digital output 7 d8 33 adc digital output 8 d9 34 adc digital output 9 d10 35 adc digital output 10 d11 36 adc digital output 11 (msb) ognd2 37 digital output ground 2 v cco2 38 digital outputs supply voltage 2 oe 39 output enable control input (low = outputs active; high = outputs in high-impedance) agnd6 40 analog ground 6 v cca6 41 analog supply voltage 4 stdby 42 standby mode control input (low = tda9962 active; high = tda9962 standby) blk 43 blanking control input clpob 44 clamp pulse input at optical black shp 45 preset sample-and-hold pulse input shd 46 data sample-and-hold pulse input clk 47 data clock input clpdm 48 clamp pulse input at dummy pixel table 3: pin description continued symbol pin description
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 6 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8. limiting values [1] all supplies are connected together. 9. thermal characteristics table 4: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cca analog supply voltage [1] - 0.3 + 4.5 v v ccd digital supply voltage [1] - 0.3 + 4.5 v v cco digital outputs supply voltage [1] - 0.3 + 4.5 v d v cc supply voltage difference between v cca and v ccd - 0.5 + 0.5 v between v cca and v cco - 0.5 + 1.2 v between v ccd and v cco - 0.5 + 1.2 v v i input voltage referenced to agnd - 0.3 + 6.5 v i o data output current - 10 ma t stg storage temperature - 55 + 150 c t amb ambient temperature - 20 + 75 c t j junction temperature -+ 150 c table 5: thermal characteristics symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 76 k/w
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 7 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. 10. characteristics table 6: characteristics v cca =v ccd = 3.0 v; v cco = 2.5 v; f pix = 30 mhz; t amb = - 20 to +75 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v cca analog supply voltage 2.7 3.0 3.6 v v ccd digital supply voltage 2.7 3.0 3.6 v v cco digital outputs supply voltage 2.2 2.5 3.6 v i cca analog supply current all clamps active - 41 - ma i ccd digital supply current - 2.0 - ma i cco digital outputs supply current c l = 10 pf on all data outputs; input ramp of 800 m s duration - 0.5 - ma digital inputs pins shp, shd and clk (referenced to dgnd) v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2.0 - 5.5 v i i input current 0 v i 5.5 v - 3 -+ 3 m a c i input capacitance -- 2pf pins clpdm, clpob, sen, sclk, sdata, stby, oe, blk and vsync v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2.0 - 5.5 v i i input current 0 v i 5.5 v - 2 -+ 2 m a clamps global characteristics of the clamp loops t w(clamp) clamp active pulse width in number of pixels pga code = 255 for maximum 8 lsb error; c cpcds =1 m f 15 -- pixels input clamp (driven by clpdm) g m(cds) cds input clamp transconductance - 15 - ms correlated double sampling (cds) v i(cds)(p-p) maximum peak-to-peak cds input amplitude (video signal) v cc = 2.85 v 650 -- mv v cc 3 3.0 v 800 -- mv v reset(max) maximum cds input reset pulse amplitude -- 1.5 v i i(in) input current into pin in at ?oating gate level -- 3 m a c i input capacitance - 2 - pf t cds(min) cds control pulses minimum active time v i(cds)(p-p) = 800 mv black-to-white transition in 1 pixel with 98.5% v i recovery 11 -- ns
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 8 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. t h(in;shp) cds input hold time (pin in) compared to control pulse shp see figure 3 and 4 3 -- ns t h(in;shd) cds input hold time (pin in) compared to control pulse shd see figure 3 and 4 3 -- ns ampli?er dr pga pga dynamic range see figure 7 and ta bl e 7 - 24 - db d g pga pga gain step 0.08 0.10 0.12 db analog-to-digital converter (adc) dnl differential non linearity f pix = 30 mhz; ramp input - 0.5 0.9 lsb total chain characteristics (cds + pga + adc) f pix(max) maximum pixel frequency 30 -- mhz f pix(min) minimum pixel rate o ccd(max) = 100 mv -- 1 mhz o ccd(max) = 200 mv -- 2 mhz t clkh clk pulse width high 15 -- ns t clkl clk pulse width low 15 -- ns t d(shd;clk) time delay between shd and clk see figure 3 and 4 - 10 - ns t su(blk;shd) set-up time of blk compared to shd see figure 3 and 4 5 -- ns v i(in)(fs) video input dynamic signal for adc full-scale output pga code = 00 - 800 - mv pga code = 255 - 50 - mv n tot(rms) total noise from cds input to adc output (rms value) see figure 8 [1] pga code = 00 - 1.4 - lsb pga code = 96 - 2.3 - lsb e in(rms) equivalent input noise voltage (rms value) pga code = 255 - 125 -m v pga code = 96 - 150 -m v o ccd(max) maximum offset between ccd ?oating level and ccd dark pixel level - 200 -+ 200 mv digital-to-analog converter (ofdout dac) v ofdout(p-p) additional 8-bit control dac (ofd) output voltage (peak-to-peak value) r i =1m w- 1.0 - v v ofdout(0) dc output voltage for code 0 - agnd - v v ofdout(255) dc output voltage for code 255 - agnd + 1.0 - v tc dac dac output range temperature coef?cient - 250 - ppm/ c z ofdout dac output impedance - 2000 -w i ofdout dac output current drive static -- 100 m a table 6: characteristics continued v cca =v ccd = 3.0 v; v cco = 2.5 v; f pix = 30 mhz; t amb = - 20 to +75 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 9 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. [1] noise ?gure includes the internal input buffer circuit. digital outputs (f pix = 30 mhz; c l = 10 pf); see figure 3 and 4 v oh high-level output voltage i oh = - 1ma v cco - 0.5 - v cco v v ol low-level output voltage i ol = 1 ma 0 - 0.5 v i oz output current in 3-state mode 0.5 v < v o xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. preliminary data rev. 03 12 september 2002 10 of 24 shp and shd should be aligned at optimum with the ccd signal. samples are taken at the falling edge. recommended placement for clk rising edge is between the falling edge of shd and the rising edge of shp. fig 3. pixel frequency timing diagram; all polarities active high. n 0.8 v 2.0 v n + 1 n - 4 n - 3 n - 2 n - 1 n + 2 n + 3 n + 4 n + 5 t cds(min) t clkh t h(in;shp) 0.8 v 0.8 v 0.8 v 0.8 v t h(in;shd) 2.0 v t cds(min) t d(shd;clk) t su(blk;shd) 2.0 v 2.0 v 2.0 v mce028 in shp shd clk data blk t h(o) t d(o) 50% 2.0 v n adc clamp code
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. preliminary data rev. 03 12 september 2002 11 of 24 shp and shd should be aligned at optimum with the ccd signal. samples are taken at the rising edge. recommended placement for clk falling edge is between the rising edge of shd and the falling edge of shp. fig 4. pixel frequency timing diagram; all polarities active low. n 2.0 v 2.0 v t cds(min) t clkl t h(in;shp) 0.8 v 0.8 v 0.8 v 0.8 v t h(in;shd) 0.8 v 0.8 v t cds(min) t d(shd;clk) t su(blk;shd) 2.0 v 2.0 v 2.0 v mce029 in shp shd clk data blk t h(o) t d(o) n 50% adc clamp code n + 1 n - 4 n - 3 n - 2 n - 1 n + 2 n + 3 n + 4 n + 5
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 12 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 5. dac voltage output as a function of dac input code. fce508 0 ofdout dac voltage output (v) 1.0 0 255 ofdout control dac input code fig 6. line frequency timing diagram. mce025 blk (active high) clpob (active high) clpdm (active high) pgaout video optical black clpob window horizontal flyback dummy video blk window clpdm window
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 13 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. full-scale at the adc input is reached at v i(cds)(p-p) = 800 mv; pga code 0. to use 36 db gain range refer to ta bl e 7 , address 0100. fig 7. total gain from cds input to adc input as a function of pga control code. 0 64 192 320 448 pga input code 128 total gain (db) 256 384 511 42 30 6 0 12 24 36 18 mce026 1.9 37.9 gain db () 1.9 36 pgacode 383 ------------------------- ? ?? db [] + = noise measurement at adc outputs: coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. front-end works at 30 mpixels with line of 1024 pixels whose ?rst 40 are used to run clpob and the last 40 for clpdm. data at the adc outputs are measured during the other pixels. as a result of this, the standard deviation of the codes statistic is computed, resulting in the noise. no quantization noise is taken into account. fig 8. typical total noise performance as a function of pga gain. 64 0 192 128 pga code 255 mce027 n tot(rms) (lsb) 5 4 7 11 10 9 8 6 3 2 0 1
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 14 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. first logic layer (dff) is clocked by the ?rst falling sclk edge after the rising sen edge. second logic layer is clocked by the load signal; this signal depends on the vsync signal. if vertical sync is not available, vsync should be connected to sen. fig 9. serial interface block diagram. ofdout dac latches pga gain latches adc clamp latches control pulse polarity latches load latch selection sd0 s data sclk sen lsb msb 8-bit dac mce030 pga control adc clamp control control pulses polarity settings sd2 sd1 sd3 sd4 sd5 12 sd6 shift register sd7 sd8 sd9 sd10 sd11 8 9 7 10 a0 a1 a2 a3 vsync flip-flop flip-flop flip-flop conditioning vsync t su1 =t su2 =t su3 = 10 ns (min.); t hd4 =t hd5 =t hd6 10 ns (min.). fig 10. loading sequence of control input data via the serial interface. mce031 sdata sclk sen vsync sd11 a1 a2 a3 a0 sd9 sd10 sd7 sd6 sd5 sd4 sd3 msb lsb sd2 sd1 sd0 t hd5 t su3 t su1 t hd6 t hd4 t su2 sd8
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 15 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. table 7: serial interface programming address bits data bits sd11 to sd0 a3 a2 a1 a0 0 0 0 0 pga gain control (sd7 to sd0) 0001dac ofdout output control (sd7 to sd0) 0 0 1 0 adc clamp reference control (sd6 to sd0); from code 0 to 127 0 0 1 1 control pulses (pins shp, shd, clpdm, clpob, blk and clk) polarity settings; sd2, sd6, sd7 and sd9 should be set to logic 1; for sd6 and sd7 see ta bl e 9 and 10 0 1 0 0 sd7 = 0 by default; sd7 = 1 for 36 db pga gain range but noise and clamp behaviour are not guaranteed other addresses test modes (do not use in normal application) table 8: polarity settings symbol pin serial control bit active edge or level shp and shd 45 and 46 sd4 1 = high; 0 = low clk 47 sd5 1 = rising; 0 = falling clpdm 48 sd0 1 = high; 0 = low clpob 44 sd1 1 = high; 0 = low blk 43 sd3 1 = high; 0 = low vsync 20 sd8 0 = rising; 1 = falling table 9: standby control using pin stdby bit sd7 of register 0011 stdby adc digital outputs sd11 to sd0 i cca + i ccd (typ.) 1 1 last logic state 1.5 ma 0 active 43 ma 0 1 active 43 ma 0 test logic state 1.5 ma table 10: output enable selection using output enable pin ( oe) bit sd6 of register 0011 oe adc digital outputs sd9 to sd0 1 0 active binary 1 high-impedance 0 0 high-impedance 1 active binary
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 16 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. 11. application information (1) pins sen and vsync should be interconnected when vertical sync signal is not available. (2) input signals in, shd and shp must be adjusted to comply with timing signals t h(in;shp) and t h(in;shd) (see section 10 characteristics ). (3) as an internal buffer is incorporated, depending on the ccd output impedance, an external input buffer may not be necessary and consequently power savings can be made. fig 11. application diagram. fce514 1 2 3 4 5 6 7 8 9 10 11 36 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 35 34 33 32 31 30 29 28 27 26 12 25 tda9962 d11 d10 d9 d8 d6 d5 d4 d3 d2 v cco v cca1 v cca2 agnd1 agnd2 in agnd3 cpcds1 ofdout test d7 shp shd clpob blk v cca6 agnd6 stdby clpdm ognd2 oe v cco2 clk cpcds2 dclpc agnd5 v cca3 v cca4 v cca5 v ccd1 v cco1 sclk sen vsync sdata agnd4 dgnd1 ognd1 serial interface v cca v cca ccd (2)(3) v cca v cco 100 nf 100 nf 100 nf v ccd 100 nf v cca 100 nf 100 nf v ccd 100 nf 1 m f 1 m f 1 m f 1 m f (1) (2) (2) d0 d1 v ccd
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 17 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. (1) the external input buffer can be omitted for ccds with low output impedance, for ccds with high output impedance, a small current (around 1 ma) is needed. fig 12. typical imaging application. ccd 12-bit data bus tda9962 (1) clamp signals clock signals mce032 digital signal processor pulse pattern generator horizontal and vertical driver
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 18 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. 11.1 power and grounding recommendations care should be taken to minimize the noise when designing a printed-circuit board for applications such as pc cameras, surveillance cameras, camcorders and digital still cameras. for the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as classical operational ampli?ers) must be taken into account, particularly with respect to power and ground connections. the connections between the ccd interface and the cds input should be as short as possible and a ground ring protection around these connections can be bene?cial. separate analog and digital supplies provide the best performance. if it is not possible to do this on the board then the analog supply pins must be decoupled effectively from the digital supply pins. the decoupling capacitors must be placed as close as possible to the ic package. in a two-ground system, in order to minimize the noise through package and die parasitics, the following recommendation must be implemented. ? the ground pin associated with the digital outputs must be connected to the digital ground plane and special care should be taken to avoid feedthrough in the analog ground plane. the analog and digital ground planes must be connected together with an inductor as closely as possible to the ic in order for them to have the same dc voltage. ? the digital output pins and their associated lines should be shielded by the digital ground plane which can then be used as a return path for digital signals.
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 19 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12. package outline fig 13. sot313-2. unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 99-12-27 00-01-19 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 20 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. 13. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 14. soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 14.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c small/thin packages. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board.
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 21 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 14.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [4] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [5] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [6] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. table 11: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable [3] suitable plcc [4] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [4][5] suitable ssop, tssop, vso not recommended [6] suitable
philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras preliminary data rev. 03 12 september 2002 22 of 24 9397 750 10167 ? koninklijke philips electronics n.v. 2002. all rights reserved. 15. revision history table 12: revision history rev date cpcn description 03 20020912 - preliminary speci?cation; third version 02 20000804 - objective speci?cation; second version 01 20000501 - objective speci?cation; initial version
9397 750 10167 philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras ? koninklijke philips electronics n.v. 2002. all rights reserved. preliminary data rev. 03 12 september 2002 23 of 24 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 16. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is ava ilable on the internet at url http://www.semiconductors.philips.com. 17. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 18. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. data sheet status [1] product status [2] de?nition objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be publish ed at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a.
? koninklijke philips electronics n.v. 2002. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 12 september 2002 document order number: 9397 750 10167 contents philips semiconductors tda9962 12-bit, 3.0 v, 30 msps analog-to-digital interface for ccd cameras 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 thermal characteristics . . . . . . . . . . . . . . . . . . . 6 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 application information . . . . . . . . . . . . . . . . . . 16 11.1 power and grounding recommendations . . . . 18 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 13 handling information . . . . . . . . . . . . . . . . . . . . 20 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14.2 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20 14.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 21 14.5 package related soldering information . . . . . . 21 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 16 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 23 17 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 18 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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